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For the past four decades, geometric scaling of silicon CMOS transistors has enabled not only an exponential increase in circuit integration density -Moore's Law - but also a corresponding enhancement in the transistor performance. Simple MOSFET geometric scaling has driven the industry to date. However, as the transistor gate lengths drop below 35nm and the gate oxide thickness is reduced to 1nm, physical limitations such as off-state leakage current and power density ...
You can specify the type of files you want, for your gadget.Transistor Scaling: Volume 913: Methods, Materials and Modeling (MRS Proceedings) | From Materials Research Society. A good, fresh read, highly recommended.
